Note: The job is a remote job and is open to candidates in USA. Crossing Hurdles is seeking a Senior RTL Design Engineer. The role involves designing and documenting chip engineering problems, building reference solutions, and collaborating with a team to maintain quality standards.
Responsibilities
- Design and document realistic chip engineering problems drawn from hands-on experience, covering design, debugging, and verification work at a production level of rigor
- Build complete reference solutions including RTL, testbenches, and supporting materials using SystemVerilog/Verilog and industry-standard toolchains
- Evaluate model outputs against real engineering problems, identifying gaps in reasoning and providing structured technical feedback
- Collaborate with a team of engineers to maintain consistent quality and difficulty standards across all submitted work
- Apply deep domain knowledge across subsystem and SoC-level concerns including interface protocols, clock domain crossings, and multi-module dataflow
Skills
- Strong experience in ASIC/SoC design and/or functional verification, ideally with exposure to production silicon through tapeout
- Strong experience in SystemVerilog/Verilog with the ability to write clean, production-quality RTL and testbench code
- Strong experience with industry verification toolchains such as Synopsys VCS, Cadence Xcelium, Siemens Questa, Verdi, or open-source equivalents including Icarus Verilog, Verilator, or CocoTB
- Strong experience in at least one specialized domain: RTL design and microarchitecture, IP integration and bring-up, UVM-based functional verification, formal verification and coverage closure, PPA and synthesis optimization, or specification authoring
- Strong experience working independently with clear written communication and the ability to document complex technical problems and solutions with precision
Company Overview